1. Field of the Invention
The present invention relates to semiconductor processing technology and, in particular, concerns a spin dependent logic device that may be used to construct high-speed non-volatile static random access memory (SRAM) cells.
2. Description of the Related Art
Since the introduction of the digital computer, electronic storage devices have been a vital resource for the retention of binary data. Some conventional semiconductor electronic storage devices utilize static latch structures as storage cells, which may be referred to as Static Random Access Memory (SRAM). As is generally known in the art, a conventional SRAM latch circuit utilizes complementary metal-oxide semiconductor (CMOS) circuitry. In one aspect, CMOS SRAM circuitry typically comprises two cross-coupled inverters, wherein the simultaneous activation of two access transistors regulates the flow of current through the cross-coupled inverter circuits for read and write functions. The inverter circuit is a fundamental CMOS circuit utilized in many memory and logic devices, such as SRAM memory, set-reset (SR) flip-flops, and various logic gates. In one aspect, a common CMOS inverter circuit comprises two series connected (drain-to-drain) and matched enhancement type metal-oxide semiconductor field-effect transistor (MOSFET) devices: one n-channel MOSFET and one p-channel MOSFET. Furthermore, the input to the inverter circuit is connected to the gate of each MOSFET device, and the output of the inverter circuit is accessed between the two MOSFET devices at the drain-to-drain connection.
SRAM devices experience fast access times, which makes SRAM a desirable memory storage device. Unfortunately, this type of semiconductor Random Access Memory (RAM) requires a continuous supply of power to maintain or preserve a defined logic-state. As a result, conventional SRAM is considered volatile memory due to the fact that data may be lost with the loss of a continuous supply of power.
Alternatively, Programmable Read Only Memory (PROM) devices, such as Erasable PROM (EPROM) and Electrically Erasable PROM (EEPROM), may be used as non-volatile memory devices in place of SRAM devices. PROM devices are user-modifiable read-only memory (ROM) devices that may be repeatedly erased and reprogrammed. EPROM devices are typically erased by shining an intense ultraviolet light on the circuitry of the memory chip and then reprogrammed in a generally known manner using electrical voltage. Unfortunately, EPROM devices need to be placed in a specially designed device for erasure and programming prior to re-write, which is substantially inconvenient under most circumstances. Unlike EPROM chips, EEPROMs do not need to be placed in a specially designed device for erasure and programming for re-write. Unfortunately, an EEPROM chip typically requires erasure and re-programming in its entirety and in a non-selective manner, which takes a considerable amount of time. In addition, EEPROM devices have limited re-programmability over the life of the device, which, in most cases, re-programmability is limited to tens or hundreds of thousands of times. Other disadvantages to PROM devices include slow read and write times, which may be substantially slower than SRAM devices. Therefore, conventional PROM devices are not typically used as non-volatile random access memory.
Based on the foregoing, there currently exists a need to replace traditional volatile SRAM with an improved solid-state non-volatile memory device that has the speed of conventional SRAM with the logic state preservation of PROM devices. Furthermore, there also exists a need to develop non-volatile memory devices that may be used in conventional applications while still maintaining a high-density fabrication process and technique.